1.To simulate the operation of a circuit used to create an edge-triggered D flip-flop.
2.To test the operation of a 74LS74 D flip-flop and compare the operation with the predicted behavior.
3.To describe and simulate the operation of edge-triggered D-type and J-K flip-flops using VHDL.
4.To test the operation of a 74LS112 J-K flip-flop and compare the operation with the predicted behavior.
Why is the condition when both and are LOW considered illegal?
How does the value you measured for tsetup compare with value specified in the 74LS74 data sheet? You may need to go on-line to find this value
Why were the LEDs removed before making the propagation delay measurements?
Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (PRE) is synchronous instead of asynchronous. The clear (CLR) remains asynchronous